The VHDL-AMS (Very high speed integrated circuits Hardware Description Language – Analog-Mixed Signal) is a standard hardware description language (standard IEEE 1076.1-1999).

The designer benefits using VHDL-AMS:

• Standard, therefore non-proprietary and independent of selected software suppliers. It is therefore used for the seamless exchange of data/models between the different project participants.
• Multidisciplinary, its native multi-domain approach provides for easy communication between the different scientific disciplines: an electrics engineer, a mechanical engineer or even a chemist may now be used for modelling its part of a device.
• Multi-level, multi-abstraction. VHDL-AMS provides mechanisms used to manage both the behavioural abstractions. The models created with VHDL-AMS may therefore both be descriptive and predictive.
• Mixed simulation, it jointly authorises modelling in continuous time (analog) and on discrete events (logic), or a mixture of the two.
• Processing of implicit equations and through them, the use of generalized Kirchhoff’s laws, the basis of implicit relations between the different nodes of a system. Writing equations therefore becomes natural for the designer (engineers language).